Transistor logic circuits



Jan. 11, 1966 R. E. BOHN ETAL 3,229,119

TRANSISTOR LOGIC CIRCUITS Filed May 17, 1963 3 Sheets-Sheet 1 OUTPUTINPUTS l INPUTS ISZ RICHARD E. BOHN and RICHARD C. SIRRINE,

INVENTORS.

AGENT.

Jan. 11, 1966 E. BOHN ETAL 3,229,119

TRANSISTOR LOGIC CIRCUITS Filed May 17, 1,963 3 Sheets-Sheet 2 OUTPUTOUTEUT RICHARD E. BOHN and RICHARD C. SIRRINE,

INVENTORS.

AGENT.

Jan. 11, 1966 E. BOHN ETAL 3,229,119

TRANSISTOR LOGIC CIRCUITS Filed May 17, 1963 3 Sheets-Sheet 5 INPUT A2INPUT A, INPUT 5 45a 35 3O 45b 34 40 m Q 3 P+ [f N+ 3 [F l G. 5 RICHARDE. BOHN and RICHARD c. SIRR/NE,

INVENTORS.

AGENT.

United States Patent 3,229,119 TRANSISTOR LOGIC CIRCUITS Richard E.Bohn, Danvers, and Richard C. Sirrine, Winchester, Mass, assignors toSylvania Electric Products Inc, a corporation of Delaware Filed May 17,1963, Ser. No. 281,183 8 Claims. (Cl. 307-885) This invention relates tologic circuits employing transistors. More particularly, it is concernedwith digital information handling circuits in which transistors areemployed for switching, amplifying, inverting, and output level voltagesetting.

The operating requirements for circuits employed in performing logicfunctions are becoming more stringent as the art of digital computersand data processing equipment advances. In particular, the time requiredfor a circuit to perform a logic operation is a limiting factor on thedata handling capability of computing apparatus. Problems are alsoencountered in providing circuits which are immune to noise, whethergenerated within or externally of the circuit. Logic circuits may alsobe restricted in their usefulness because of limited fan-out. Fan-out isa measure of the number of succeeding logic circuits which can beoperated with parallel input connections to the output connection of thecircuit.

Size is also a significant consideration in the high speed dataprocessing art. Logic circuits have been designed for fabrication withina single chip or die of semiconductor material. With these so-calledintegrated circuits the size of a complete logic circuit is reduced tothat of a single standard electrical component. However, integratedlogic circuits have certain problems in addition to those common tologic circuits in general. The ability to dissipate power is limited,and this situation may result in restricting the circuit to low fan-out.Since all of the components are located on a single small piece ofsemiconductor material there are problems of interaction between theindividual components. In addition, the available electrical current maybe limited and certain of the components may be deprived of the currentnecessary for proper operation.

It is an object of the present invention, therefore, to provide improvedlogic circuits.

It is a more specific obiect of the invention to provide logic circuitswhich have improved operating characteristics and which are amenable tofabrication as integrated circuits.

It is also an object of the invention to provide an integrated logiccircuit incorporating an element which combines the electrical functionsof more than one type of electrical component.

Briefly, logic circuits in accordance with the foregoing objects of theinvention include an input circuit means which is adapted to produce asignal in response to a predetermined signal condition at its input. Afirst transistor circuit means connected to the input circuit meansproduces signals at first and second output connections in response to asignal from the input circuit means. A second transistor circuit meansis responsive to a signal at the first output connection to change thevoltage level at an output terminal from a first predetermined voltageoutput level to a second predetermined voltage level. The secondtransistor circuit means is also adapted to restore the voltage level atthe output terminal to the first predetermined voltage level in responseto termination of the signals at the first and second outputconnections.

it is a feature of the invention to provide an integrated circuitelement in the second transistor circuit means which combines thefunctions of a transistor and a re- "ice sistor with the resistorconnected between the base and the collector of the transistor. Theelement also produces premature saturation effects in the transistorupon the existence of short circuit conditions in the collectoremittercircuit.

Additional objects, features, and advantages of logic circuits accordingto the invention will be apparent from the following detailed discussionand the accompanying drawings wherein:

FIG. 1 is a schematic diagram of a dual NAND logic circuit gateaccording to the invention,

FIG. 2 is a schematic diagram of a NAND-OR logic circuit according tothe invention,

FIG. 3 is a schematic diagram of a set-reset flip-flop circuit accordingto the invention,

FIG. 4 is a plan view of the dual NAND logic circuit shown schematicallyin FIG. 1 embodied as an integrated circuit in a die of semiconductormaterial,

FIG. 5 is an elevational view in cross section of a portion of thesemiconductor die of FIG. 4 taken along lines 5-5 of FIG. 4 showing anintegrated circuit element which combines the functions of a transistorand resistor in a single element, and

FIG. 6 is a circuit diagram of the equivalent circuit of the portion ofthe integrated circuit of FIG. 4 shown in the cross sectional view ofFIG. 5.

FIG. 1 is a schematic circuit diagram of a dual NAND logic circuit gateaccording to the invention. The circuit network as shown includes twoidentical circuits 10 and 11 each of which is an independent NAND logiccircuit.

The first NAND circuit 10 may be considered as being 0 1' when no inputsignals are being applied at the input terminals A A and A The voltageat the terminals is at a low level and in logic terms may be called afalse voltage. Under these conditions the voltage at the output terminalA is at a high level which may be termed a true voltage. Only during theconcurrent occurrence of true voltage input signals at all three inputterminals A A and A; does the circuit turn on" and produce a low levelfalse voltage at the output terminal A. When a false voltage exists atone or more of the input terminals A A and A the circuit is off and atrue voltage is produced at the output terminal A.

The low level or false voltages and the high level or true voltagesproduced at the output terminal are of the same value as those appliedat the input terminals. Therefore, logic circuits according to theinvention can be connected together serial and in parallel in anydesired combination in order to process digital information.

The NAND logic circuit 10 of FIG. 1 includes an input circuit sectionwhich performs an AND logic function. In the particular circuit shown anNPN input transistor T has its base electrode connected through aresistance R to a source of positive voltage V The input to thetransistor includes three emitter electrodes each of which is connectedto an input terminal A A and A The collector electrode of the inputtransistor T provides the output connection from the input section.

The logic function of inverting a signal from the input section inaddition to the functions of amplifying and output voltage level settingare performed by a transistorized circuit section. A first NPNtransistor T in this section has its base electrode connected to theoutput connection from the input section. Its collector electrode isconnected through a collector resistance R to the positive voltagesupply V The emitter electrode is connected through a pull-downresistance R to a source of negative voltage V An NPN output transistorT has its base electrode connected to the emitter electrode 3 of thefirst transistor T its emitter electrode connected to ground, and itscollector electrode connected to the output terminal A of the circuit.

The amplifying and inverting section also includes an NPN voltagesetting transistor T which has its base electrode connected to thecollector of transistor T and its collector electrode connected to thepositive voltage source V The emitter electrode of the voltage settingtransistor is connected through a diode D to the output terminal A. Thediode is connected for forward conduction from the emitter electrode tothe output terminal A.

The NAND logic circuit of FIG. 1 operates in the following manner. Whenthe input terminals A A and A are all at the low voltage false level thecircuit is oif and a high voltage true level is produced at the outputterminal A. The low voltage level at an input terminal may be caused bya low impedance between the terminal and ground. In this situationcurrent flow from the supply V through the input resistance R thebaseemitter diode of the transistor T and the low impedance connected tothe input terminal produces a low voltage at the terminal. The lowimpedance between the input terminal and ground may be caused, forexample, by an on condition in a preceeding logic circuit according tothe invention to which the input terminal is connected as will beapparent from the explanation hereinafter.

With the emitters of the input transistor T at a low voltage level,current from the supply V flows through the input resistance R, and thebase-emitter diodes of the transistor. The greatest voltage drop occursacross the resistance R causing the voltage at the base of the inputtransistor T to be relatively low. Conduction in the collector circuitis thus slight and the voltage at the collector of the transistor islow.

The first transistor T of the inverting and amplifying section of thecircuit is connected in series with collector resistance R and pull-downresistance R between the positive voltage supply V and the negativevoltage supply V The magnitude of the voltage of the negative source Vis slightly less than that of the positive source V and the resistance Ris approximately five times the resistance of the resistance R Thisbiasing arrangement is such that when the no signal low voltage from thecollector or" the input transistor T is applied at the base of thetransistor T a small current flows through the transistor and the twoseries connected resistances R and R A fairly high voltage is thusestablished at the collector of transistor T and a fairly low voltage,slightly below ground, at the emitter.

Since the voltage produced at the emitter of the transistor T is low,the output transistor T is biased in the non-conducting condition. Inthis condition the transistor presents a high impedance between theoutput terminal A and ground.

The voltage at the collector of the transistor T is applied to the baseof the voltage setting transistor T Under normall otf conditions of thecircuit the small leakage current of the output transistor T flowsthrough the voltage setting transistor T although both transistors canbe considered as being substantially non-conductive. The voltage dropacross the forward resistance of the base-emitter diode of thetransistor T and that of the series connected diode D establishes thevoltage level at the output terminal A.

As is well understood in the art of semiconductor logic circuits, whenthe voltage signal level at any one of the input terminals A A or A israised to the high voltage true level as by virtue of its beingconnected to the output terminal of a logic circuit which is turned 01f,no change occurs at the collector electrode of the input transistor TCurrent flow through the base-emitter diode to the input terminal stops,Since the diode is reversed biased. However, current continues to flowthrough the input resistance R and through the other base-emitter diodesof the transistor T Thus, the voltage, at the base electrode of theinput transistor T is not changed, and the logic circuit remains off.This situation continues to exist regardless of the number of inputterminals so long as any one of them is biased at the low voltage falselevel.

When the voltage levels at all three input terminals A A and A are atthe high voltage true level concurrently, current from the supply V canno longer flow in the same manner because all the base-emitter diodes ofthe transistor T are reverse biased. As the flow of current is reducedthe voltage at the base of the input transistor T rises thereby causingconduction through the transistor and increasing the voltage on thecollector. This action at the base electrode of the transistor T causesgreatlyincreased conduction through that transistor.

The increased current flow through the transistor T and its seriesconnected resistances R and R lowers the voltage at the collectorelectrode and raises the voltage at the emitter electrode. The outputtransistor T is thereby biased to conduction providing a low impedancepath between the output terminal A and ground and establishing a lowvoltage false level at the output terminal.

The voltage at the base electrode of the voltage setting transistor T issuch as to insure that the transistor remains in a non-conductingcondition maintaining the output terminal A at a low voltage signallevel.

Upon termination of the high voltage level signal at one or more of theinput terminals A A or A a base-emitter diodeof the input transistor Tbecomes forward biased permitting current flow through the inputresistance R The increased voltage drop across the resistance R lowersthe potential at the base of the input transistor T thereby reducingconduction in the collector circuit and the potential at the collector.This condition biases the transistor T so that only slight conductionoccurs through the transistor and series connected resistances R and RThe voltage at the collector of the transistor T is thereby increasedand that at the emitter is reduced.

The reduced voltage at the emitter electrode of transistor T biases thebase of the output transistor T so as to render that transistornon-conducting. The output transistor ,T thus presents a high impedancebetween the output terminal A and ground. The increased voltage appliedat the base of the voltage setting transistor T together with the lowvoltage level existing at the output terminal A causes that transistorto conduct. The transistor conducts heavily until the voltage at theoutput terminal A is restored to the level established by the voltage atthe transistor base less the forward biasing voltage drop across thebase-emitter diode of the transistor and the diode D The voltage at theoutput terminal A fails to revert to the high level immediately upontermination of current flow throught he output transistor T because ofvarious capacitance elfects on the output terminal A and its externalconnections as indicated by the capacitance symbol 12 shown in dashedlines. In order for the voltage at the output terminal A to rise, thisload capacitance must be charged. The heavy flow of current from thesupply V through the voltage setting transistor T charges the loadcapacitance very rapidly. When the output terminal A reaches the uppervoltage true level as established by the voltage at the base of thevoltage setting transistor T the transistor no longer conducts and thelogic circuit is o The second logic circuit 11 of the dual NAND gateoperates in exactly the same manner as does the first circuit 10providing a NAND logic function having three input terminals B B and Band an output terminal B.

FIG. 2 is a schematic circuit diagram of a NAND-OR circuit gate 15 inwhich alow voltage false level is produced at the output terminal C whenthere is a coincidence of high voltage level input signals at inputterminals C C and C or when there is a coincidence of high voltage levelinput signals at input terminals C C C,;. When neither of theseconditions exists at the input, a high voltage true level is produced atthe output terminal C.

The input terminals C C and C are connected to the three emitterelectrodes of a first input transistor T This transistor is connected ina manner similar to the input transistor of FIG. 1. Its base electrodeis connected through a first input resistance R to the positive voltagesource V and its collector electrode is connected directly to the baseof a first transistor T in the amplifying and inverting section of thecircuit. The input terminals C C and C are similarly connected to theemitter electrodes of a second input transistor T having its baseelectrode connected through a second input resistance R to the voltagesource V and its collector electrode connected to the base of a secondtransistor T in the amplifying and inverting section.

The emitters and the collectors of the first two transistors T and T inthe amplifying and inverting section are Connected directly together.The common collector connection is connected through the collectorresistance R to the positive voltage source V The common emitterconnection is connected through a base pull-down resistance R to asource of negative volt age V An output transistor T is connected in amanner similar to the output transistor in the circuit of FIG. 1. Thebase is connected to the common emitter connection of transistors T andT the emitter is connected directly to ground, and the collector isconnected directly to the output terminal C.

A voltage setting transistor T is also connected in the circuitsimilarly to the voltage setting transistor of FIG. 1. The base isconnected to the common collector connection of the two transistors Tand T and the collector is connected directly to the positive voltagesource V The emitter is connected through a diode D to the outputterminal C.

A coincidence of high voltage true signals at the input terminals C Cand C causes increased conduction through the first transistor T of theamplifying and inverting section in accordance with the explanation ofthe operation of the circuit of FIG. 1. The signal produced at theemitter of transistor T causes the output transistor T to conductthereby reducing the voltage at the output terminal C to the low falselevel.

Similarly a coincidence of true input signals at the input terminals C Cand C causes increased conduction through transistor T This conditionaffects the base of the output transistor T switching that transistor toa high conduction condition and reducing the voltage at the outputterminal C to the low false level. Thus, an increased conductioncondition in either transistor Tog or T causes the logic circuit to turnon and a low voltage false level to be produced at the output terminalC.

When a change occurs in the voltage signal levels at the input terminalsso that signals from one or both of the input transistors T and T becometerminated and no signals are transmitted to transistors T and Tconduction through transistors T and T is slight. The resultingconditions at the common emitter connection and at the common collectorconnection cause the output transistor T to become non-conductive andthe voltage setting transistor T to become conductive. Current flowsthrough the voltage setting transistor charging the load capacitanceuntil the output terminal C is restored to the high voltage true level.The manner of operation of the circuit to obtain rapid turning otf isthe same as that previously described in the discussion of the logiccircuit of FIG. 1.

A set-reset flip-flop network is illustrated in the circuit diagram ofFIG. 3. The network includes two cross-coupled NAND circuits 21 and 22according to the invention together with pulse-level input gates. Whenthe network is functioning, one of the NAND circuits is on while theother is oif. The operating states of the circuits are reversed by asuitable combination of input signal conditions serving to turn the oncircuit oil.

The first NAND logic circuit 21 is the same as either of the NANDcircuits of FIG. 1. It includes a three input AND section having a threeemitter transistor T with its base connected through a resistance R to apositive voltage source V Input connections are made to the emitters ofthe transistor and the output is taken from the collector.

The output for the AND section is applied to the base of a firsttransistor T in the amplifying and inverting section of the circuit. Thecollector of transistor T is connected through a resistance R to thepositive voltage source V and its emitter is connected through aresistance R to a negative voltage source V An output transistor T hasits base connected to the ernitter of transistor T its emitter connectedto ground, and its collector connected to an output terminal D. Avoltage setting transistor T has its base connected to the collector oftransistor T its collector connected to the positive voltage source Vand its emitter connected through a diode D to the output terminal D.

A pulse-level input gate is connected to one of the emitters of the ANDsection transistor T The gate includes an input gate transistor T havingits collector connected to the emitter of transistor TD and its baseconnected through a resistance R to ground. The emitter of the inputgate transistor T is connected to a set terminal, and the base isconnected through a ca acitance C to a first clock pulse terminal CP Thesecond NAND logical circuit 22 is the same as the first circuit 21. Athree emitter AND section transistor T is connected to an amplifying andinverting section including transistor T an output transistor T and avoltage setting transistor T The transistors are suitably connected toeach other and to resistances and voltage sources to provide the propervoltage level at the output terminal E as explained previously.

A pulse-level input gate is connected to one of the emitters of the ANDsection transistor T of the second NAND logic circuit. The collector ofthe input gate transistor T is connected to the one emitter oftransistor T and its base is connected through a resistance R to ground.The emitter of transistor T is connected to a reset terminal and thebase is connected through a capacitance C to a second clock pulseterminal CP The inputs and outputs of the two NAND logic circuits arecross-coupled by a connection from the output terminal D of the firstcircuit to one of the emitters of the AND section transistor T of thesecond circuit and by a connection from the output terminal E of thesecond circuit to one of the emitters of the AND section transistor T ofthe first circuit. The third emitter of the AND section transistor T ofthe first circuit is connected to a D.C. set" terminal and the thirdemitter of the corresponding transistor T in the second circuit isconnected to a DC. reset terminal.

In order to explain the operation of the flip-flop network 20, let it beassumed that the first NAND logic circuit 20 is on and the second NANDlogic circuit 22 is oif. In order for this condition to exist, highvoltage level signals must be present at all three emitters of the ANDsection transistor T The DC. set and DC. reset terminals are biased atthe high voltage level by a continuous DC. bias which is altered only topreset the conditions of the network cricuits prior to digitaloperation. Another emitter of transistor T is connected to the outputterminal E of the second NAND logic circuit, and since the secondcircuit is oil a high voltage level signal is present at the emitter.

The third emitter of the AND section transistor T is connected-to theinput gate transistor T There are two input connections to the inputgate transistor; the set terminal and the first clock pulse terminal CPThe voltage level applied at the set terminal is either the low voltagefalse level or the high voltage true level. The clock pulse terminal CPis normally biased at a low level near ground, and positive clock pulsesare periodically applied to the terminal. During the time intervalbetween clock pulses, the input gate transistor T remains non-conductiveregardless of whether the voltage level at the set terminal is high orlow. Thus, the input gate transistor T D is normally non-conductive anda high voltage level is established at the third emitter of the ANDsection transistor T In normal operation the flip-flop network istriggered to turn the first NAND logic circuit 21 off and the secondlogic circuit 22 on by the arrival of a positive clock pulse at theclock pulse terminal CP while a low voltage level signal is beingapplied at the set terminal. The rising waveform of the clock pulse isdifferentiated by the capacitance C and resistance R combination toprovide a positive signal at the base of the input gate transistor T Ifa high voltage level signal is being applied at the set terminal, thesignal at the transistor base ha no effect and the transistor remainsnon-conductive. However, if a low voltage signal is being applied at theset terminal, the signal at the base of the input transistor T biasesthat transistor to conduction.

Momentary conduction-through the input gate transistor T 5 caused by alow voltage signal at the set terminal during the occurrence of apositive clock pulse at the clock pulse terminal'CP causes a momentarydrop in the voltage level at the emitter of the AND section transistor Tto which the collector of transistor T is connected. As previouslyexplained in describing NAND logic circuits according to the invention,this condition causes the first NAND logic circuit 21 to turn off. Thevoltage at the output terminal B is thereby raised to the high voltagelevel.

In the second NAND logic circuit 22 the D.C. reset terminal is held atthe high voltage level as explained previously and since the pulse-levelinput gate is not conducting, theernitter of the AND section transistorT connected to the input gate transistor T is at the high voltage level.Therefore, when a high voltage level is established at the third emitterof the AND section transistor T by the connection to the output terminalD, the second NAND logic circuit 22 is turned on. The voltage at theoutput terminal E is thereby reduced to the low voltage level. Thisvoltage level is applied to an emitter of the AND section transistor Tof the first logic circuit 21, thus maintaining that circuit off afterthe clock pulse at the clock pulse terminal CP has terminated and theinput gate transistor has returned to the non-conducting condition.

The operating states of the two NAND logic circuits may be reversedagain by a positive going clock pulse arriving at the second clock pulseterminal CP While the reset terminal is being held at the low voltagelevel. Current flow through the input gate transistor T lowers thevoltage on the emitter of the AND section transis tor T causing thesecond logic circuit to turn off, and the connection between the outputterminal E and the emitter of the AND section transistor T causes thefirst NAND logic circuit to turn on.

The dual NAND circuit shown schematically in FIG. 1' is'illustrated inthe form of an integrated circuit in the plan view of FIG. 4. Anelevational view in cross section of a portion of the die 30 ofsemiconductor material in which the circuit elements are fabricated isshown in FIG. 5. For ease in understanding, the reference charactersemployed in FIG. 1 are used where applicable in FIG. 4.

As can best be seen from the cross sectional view of FIG. 5 thecircuitry is fabricated byepitaxially growing layers of semiconductormaterial on a substrate and diffusing conductivity type impartingmaterials into the epitaxial layers. In actual practice hundreds ofintegrated circuits are fabricated simultaneously on a relatively largeslice of semiconductor material. However, for purposes of illustrationonly a single integrated circuit formed in a small portion of such aslice is shown in FIGS. 4 and 5. The substrate of semicondutcor materialis a body 30 of single crystal silicon of high resistivity P-typeconductivity. A thin layer 31 of low resistivity N-type silicon is grownon the substrate by known epitaxial techniques. Another layer 32 ofN-type silicon having higher resistivity is then grown on the firstepitaxial layer.

The various circuit elements are then fabricated by a series of steps inwhich conductivity type imparting materials are selectively diffusedinto regions of the silicon die. Known techniques of coating the surfaceof the die with a protective non-condutcive oxide layer, masking with aphoto-resistant material, and etching to provide openings in the oxidecoating through which a conductivity type imparting material may bediffused are utilized prior to each diffusion step to delineate theregions into which the conductivity type imparting material is to bediffused. A P-type conductivity imparting material is first diffusedinto the appropriate regions of the semiconductor die to provide highcondutcivity P-type isolating regions 33 for isolating the variouselectrical elements from each other. Then, a P-type conductivityimparting material is diffused into regions 34 of the N-type epitaxiallayer to provide the base regions for the transistors, the resistancecomponents, and also the anode regions of the diodes. Finally, theemitter regions of the transistors are produced by the diffusion of anN-type conductivity imparting material into regions 35 of the baseregions 34. The boundaries, or junctions, of each region of a singleconductivity type are indicated by relatively heavy lines in FIG. 4.

Following the difiusion steps, the protective oxide coating 40 isreconstituted, and openings are etched in the coating over the areas onthe surface of the die at which electrical connections are to be made tothe underlying semiconductor material. The entire urface of the die isthen coated with an adherent layer of conductive material, as by vapordeposition of aluminum. Portions of the aluminum layer are then removedby appropirate masking and etching steps to leave a pattern ofelectrical connections 45 to the circuit elements. The edges of theelectrical connections are indicated by relatively thin lines in FIG. 4.The areas at which the electrical connections make contact to electricalelements at openings in the oxide coating are designated by stippling inFIG. 4. Terminals to which the external connections of the circuit areto be made are provided by large areas 46 of the aluminum layer locatednear the edges of the die. The completed integrated circuit asillustrated in FIG. 4 may be placed in any suitable enclosure havingleads to which the terminal areas 46 may be connected.

In the version of the integrated circuit illustrated in FIG. 4 thediodes, four of the resistances, and six of the transistors aregenerally in accord with known structures of components formed bydiffusion of conductivity type imparting materials into semicondutcormaterial. Each of the voltage setting transistorsT and T and itassociated resistance R and R however, as shown in FIGS. 4 and 5 arefabricated as a single element. Although the NAND logic circuitillustrated schematically in FIG. 1 may be constructed with discreteelectrical components or as an integrated circuit in which eachelectrical function is performed by a separate element, certainadvantages are obtained by combining the voltage setting transistor withthe associated resistance in a single element. 7

The P-type region which constitutes the base of the voltage settingtransistor T is elongated relative to the base region of othertransistors. A first electrical connection 45a is made to the baseregion adjacent the baseemitter junction and a second connection 452) ismade at the end of the base region away from the emitter. This secondconnection also makes contact to the collector region of the transistor.The elongated P-type region between the connections 45a and 455 thusserves both as the resistance component R between the collector and baseof transistor T and as the base region of the transistor. The magnitudeof the resistance depends on the resistivity and dimensions of theregion.

FIG. 6 is a schematic circuit diagram of the equivalent circuit of thecombined transistor-resistor element of FIG. 5. Under normal operatingconditions as explained previously the positive supply voltage V isapplied at the connection 45b. The resistance R is thereby con nectedbetween the supply voltage and the base of the transistor, and there isa direct connection between the voltage source and the collector region.

When the logic circuit of FIG. 1 is functioning as explained previouslyin this application, the transistor T is caused to conduct by virtue ofthe termination of a signal at its base (via connection a) whichincreases the base potential while the output terminal of the circuitwhich is connected to the emitter is at a low voltage level. Heavycurrent fiows through the collector and emitter to charge the loadcapacitance and to raise the voltage level at the output terminal. Sincethe only resistance connected between the output terminal and thevoltage source is that of the heavily conducting transistor and theforward biased diode, the voltage at the output terminal is increased tothe desired level in a very short time, on the order of 8 1O seconds.

With an ordinary transistor connected to a resistance, voltage source,and output terminal in this manner, it the emitter should be held ata-low potential as by inadvertent grounding of the output terminal, thetransistor would tend to draw a heavy current. Although a transistor cansafely pass a heavy current during the few nanoseconds required tochange the load capacitance,

sustained current flow may burn out an ordinary transistor subjected tothis short circuit condition.

By virtue of the length of the current path from the connection 451')for the supply voltage at the collector of the transistor T to theemitter, however, a resistance efi'ect to sustained high current flow isproduced in the element. This effect between the connection 45b and thecollector junction of the transistor is indicated by a resistanceillustrated in phantom in FIG. 6. The short circuit current through thetransistor is reduced by the resistance effect and burnout does notoccur. The structure may also be thought of as causing a prematuresaturation effect in the transistor under conditions of sustained highcurrent flow, thereby causing a drop in the amplification factor of thetransistor and consequently limiting the collector current.

Logic circuits according to the invention provide many advantages overcircuits previously available. The time required for the circuit to becompletely turned on after a high voltage level is applied at each inputterminal is small. Even more significant, the time required forrestoring the voltage at the output terminal from the low level to thehigh level after the voltage level at an input terminal is reduced isvery rapid. This propagation delay is usually the limiting factordetermining the operating rate of known logic circuits.

The circuits disclosed are relatively immune to triggering by noise. Theamplification provided by transistors in the circuit permits a largedifference in the false and true voltage levels employed. Thus, spurioussignals are much less likely to affect the circuit.

In each circuit the output terminal is restored to the high voltagelevel by current supplied from the voltage source through the elementsof the circuit. That is, the restoring current for charging the loadcapacitance is not supplied from succeeding logic circuitry. The circultis, therefore, relatively insensitive to loading and the fan-out (numberof succeeding circuits which can be connected to the output terminal) islarge. Isolation of each circuit from the adjacent circuits eliminatesany tendency for components in one circuit to deprive a component in anadjacent circuit of current necessary for proper operation. Because ofthe current gain in the circuit and the load capacitance drivingcapability of the voltage setting transistor, 8. high input impedance isallowable at the input terminals; and, therefore, high fanout can beobtained without requiring heavy power dissipation in the circuit.

What is claimed is:

1. A logic circuit including in combination an input circuit meansadapted to produce a signal in response to a predetermined signalcondition at the input thereto,

a first transistor circuit means connected to said input circuit meansand responsive to said signal to produce signals at first and secondoutput connections,

a second transistor circuit means including a second transistorconnected to the first of said output connections, an output terminal,and a source of reference potential, and responsive to the signal at thefirst of said output connections to bias the second transistor toconduction and change the voltage level at the output terminal from afirst pedetermined voltage level to a second predetermined voltagelevel, and

a third transistor circuit means including a third tran sistor connectedto the second of said output connections and to said output terminal andresposnive to termination of the signal at the second of said outputconnections to bias the third transistor to conduction and change thevoltage level at the output terminal from said second predeterminedvoltage level to said first predetermined voltage level, and responsiveto restoration of said first prede termined voltage level at the outputterminal to bias the third transistor to non-conduction.

2. A logic circuit iolu ding in combination an input circuit meansadapted to produce a signal in response to the occurrence of apredetermined signal condition at the input thereto;

a first transistor circuit means having a first transistor with an inputelectrode connected to the input c-ircuit means and being adapted toproduce output signals at the other two electrodes of the transistor inresponse to the presence of said signal "at the input electrode;

a voltage setting transistor having its input electrode connected to oneof said other two electrodes of the first transistor and its outputelectrode connected to an output terminal, circuit means biasing saidvoltage setting transistor to produce a first predetermined voltagelevel at the output terminal during itilC absence of an output signalfrom the first transistor circuit; and

an output transistor having its input electrode connected to the otherof said other two electrodes of the first transistor and its otherelectrodes connected between the output terminal and a source ofreference potential circuit means biasing said output transistor toprovide a high impedance between the output terminal and said source ofreference potential during the absence of an output signal from thefirst transistor circuit, said circuit means also biasing said outputtransistor to provide a low impedance path between the output terminaland said source of reference potential in response to the presence of anoutput signal from said first transistor circuit thus producing a secondpredetermined voltage level at the ouput terminal;

said circuit means associated with the voltage setting transistorbiasing said voltage setting transistor to cause conduction therethroughto restore the voltage at the output terminal from the second voltagelevel to the first voltage level in response to the presence of thesecond voltage level at the output terminal during the absence of anoutput signal from the first transistor circuit, and biasing saidvoltage setting transistor to non-(conduction in response to restorationof the first voltage level at the output terminal.

3. A logical circuit including in combination an input circuit meansadapted to produce a signal at an output connection during theconcurrentoccurrence of a first voltage level at a plurality of input terminals;

a first transistor havin'gits base electrode connected to the outputconnection of the input circuit means, its emitter electrode connectedthrough a resistance to one source of reference potential, and itscollector electrode connected'through a resistance to another source ofreference potential providing a voltage drop across the transistor andthe series connected resistances whereby the absence of a. signal at theoutput connection of the input circuit means biases the first transistorto a low conduction condition;

and the presence of a signal at the output connection of the inputcircuit means biases the first transistor to a high conductioncondition;

a voltage setting transistor, voltage setting transisor circuit menasconnecting the base electrode of the voltage setting transistor to thecollector electrode of the first transistor, the collector electrode ofthe voltage setting transistor to said other source of referencepotential, and the emitter electrode of the voltage setting transistorto an output terminal, and operable to bias the voltage settingtransistor to produce the first voltage level at the output terminalwhile the first transistor is in the low conduction condition;

an output transistor, output transistor circuit means comnecting thebase electrode of the ouput transistor to the emitter electrode of thefirst transistor, the collector electrode of the. output transisor tothe output terminal, and the emitter electode of the output transistor,to a source of reference potential;

said output transistor circuit means being operable to bias the outputtransistor to a substantially no-n conducting condition while the firsttransistor is in the low conduction condition, and being operable tobias the output transistor to a high conducting condition and produce asecond voltage level at the output terminal while the first transistoris in the high conduction condition;

said voltage setting transistor circuit means being operable to bias thevoltage setting transistor to a high conducting condition in response tothe presence of the second voltage level at the output terminal whilethe first transistor is in the low conduction condtion, and beingoperable to bias the voltage setting transistor to a substantiallynon-conducting condtion in response to restoration of the first voltagelevel at the output terminal.

4. A logic circuit including in combination an input circuit meansadapted to produce a signal in response to a predetermined combinationof concurrent signals at a plurality of input terminals;

2. first transistor circuit means including a first transistor having aninput electrode connected to the input t, circuit means, said firsttransistor circuit means being ;;.-a=dapted to produce output signals atthe other two ,--.--electrodes of the first transistor in response tothe presence of a signal from said input circuit means at the inputelectrode of the first transistor;

an output transistor circut means including an output transistor havingan input electrode connected to one of said other two electrodes of thefirst transistor and its other electrodes connected between an outputterminal and a source of reference potential, said output transistorcircuit means being adapted to provide a low impedance path between theoutput terminal and said source of reference potential in response tothe presence of an output signal from first transistor circuit means;

said output transistor circuit means also being adapted to provide ahigh impedance path between the output terminal and said source ofreference potential in response to the absence of an output signal formsaid first transistor circuit means; and

voltage setting transistor circuit means including a voltage settingtransistor having an input electrode connected to the other of saidother two electrodes of the first transistor and an output electrodeconnected to said output terminal, said voltage setting transistorcircuit means being adapted to produce and maintain a predeterminedvoltage level at the output terminal in response to the termination ofan out signal from said first transistor circuit means, said voltagesetting transistor circuit means being operable to cause conductionthrough said voltage setting transistor to said output terminal so as toestablish said predetermined voltage level at the output terminal inresponse to the absence of an output signal from said first transistorcircuit means at the input electrode of the voltage setting transistorWhile said predetermined voltage level is not present at the outputterminal, and being operable to bias the voltage setting transistor tonon-conduction in response to the presence of said predetermined voltagelevel at the output terminal.

5. A logic circuit including in combination an input circuit meansadapted to produce a signal emitter electrode and the collectorelectrode during the occurrence of a signal at the output connection ofthe input circuit means.

a voltage setting transistor, circuit means connecting the baseelectrode of the voltage setting transistor to the collector electrodeof the first transistor, the collector electrode of the voltage settingtransistor to said other source of reference potential, and the emitterelectrode of the voltage setting transitor to an output terminal, andoperable to bias the voltage setting transistor to produce a firstpredetermined voltage level at the output terminal during the absence ofan output signal at the collector electrode of the first transistor;

an output transistor, circuit means connecting the base electrode of theoutput transistor to the emitter electrode of the first transistor, thecollector electrode of the output transistor to the output terminal, andthe emitter electrode of the output transistor to a source of referencepotential, and operable to bias the output transistor to provide a highimpedance between the output terminal and said last-mentioned source ofreference potential during the absence of an output signal at theemitter electrode of the first transistor, and to provide a lowimpedance path between the output terminal and said last-mentionedsource of reference potential during the occurrence of an output signalat the emitter electrode of the first transistor thus producing a secondpretetermined voltage level at the output terminal; and

said circuit means associated with the voltage setting transistor beingoperable to bias the voltage setting transistor to initiate conductiontherethrough in response to the absence of an output signal at thecollector electrode of the first transistor and the presence of thesecond predetermined voltage level at the output terminal and restorethe voltage level at the output terminal to the first predeterminedvoltage level, and operable to bias the voltage setting transistor tonon-conduction in response to restoration of the first predeterminedvoltage level at the output terminal.

6. A logic circuit including in combination a first input circuit meansadapted to produce a signal at a first output connection in response toa predetermined combination of concurrent signals at a first pluralityof input terminals,

a second input circuit means adapted to produce a signal at a secondoutput connection in response to a predetermined combination ofconcurrent signals at a second plurality of input terminals,

a first transistor circuit means including a first transsistor having aninput electrode connected to the output connection of the first inputcircuit means, said first transistor circuit means being adapted toproduce output signals at first and second output electrodes of thefirst transistor in response to the presence of a signal from said firstinput circuit means at the input electrode of the first transistor,

a second transistor circuit means including a second transistor havingan input electrode connected to the output connection of the secondinput circuit means, said second transistor circuit means being adaptedto produce output signals at first and second output electrodes of thesecond transistor in response to the presence of a signal from saidsecond input circuit means at the input electrode of the secondtransistor,

the first output electrodes of the first and second transsistors beingconnected to each other,

the second output electrodes of the first and second transistors beingconected to each other,

an output transistor circuit means including an output transistor havingan input electrode connected to the first output electrodes of the firstand second transsistors and its other electrodes connected between anoutput terminal and a source of reference potential, said outputtransistor circuit means being adapted to provide a low impedance pathbetween the output terminal and the source of reference potential inresponse to the presence of an output signal at a first output electrodeof said first and second transistors,

a voltage setting transistor circuit means including a voltage settingtransistor having an input electrode connected to the second outputelectrodes of the first and second transistors and an output electrodeconnected to said output terminal, said voltage setting transistorcircuit means being adapted to produce and maintain a predeterminedvoltage level at the output terminal during the absence of outputsignals at the second output electrodes of said first and secondtransistors, said voltage setting transistor circuit means beingoperable to cause conduction through said voltage setting transistor tosaid output terminal so as to establish said predetermined voltage levelat the output terminal in response to the absence of output signals atthe second output electrodes of the first and second transistors whilesaid predetermined voltage level is not present at the output terminal,and being operable to bias the voltage setting transistor tonon-conduction in reid sponse to the presence of said predeterminedvoltage level at the output terminal.

A logic circuit including in combination first input circuit meansadapted to produce a signal at a first output connection during theoccurrence of a predetermined combination of concurrent signals at afirst plurality of input terminals, second input circuit means adaptedto produce a signal at a second output connection during the occurrenceof a predetermined combination of concurrent signals at a secondplurality of intput terminals, first transistor having its baseelectrode connected to the output connection of the first input circuitmeans, second transistor having its base electrode connected to theoutput connection of the second input circuit means,

the emitter electrodes of the first and second transistors beingconnected to each other and through a resistance to a source of voltageof one polarity,

the collector electrodes of the first and second transistors beingconnected to each other and through a esistance to a source of voltageof the opposite polarity,

an output transistor having its base electrode connected the absence ofsignals at the output connections of the first and second input circuitmeans biasing both the first and second transistors to low conductionconditions thereby biasing the output transistor and the voltage settingtransistor to substantially nonconduction conditions, the voltagesetting transistor setting the voltage at the output terminal at a firstvoltage level,

the presence of a signal at the output connection of one of said inputcircuit means biasing the transistor connected thereto to a highconduction condition thereby biasing the output transistor to a highconduction permitting the voltage at the output terminal to change to asecond voltage level,

termination of a signal at the output connection of one of said inputcircuit means and the absence of a signal at the output connection ofthe other input circuit means biasing the first and second transistorsto low conduction conditions thereby biasing the output transistor to asubstantially non-conduction condition and biasing the voltage settingtransistor to a high conduction condition until current fiowtherethrough restores the voltage at the output terminal to the firstvoltage level and biases the voltage setting transistor to asubstantially non-conduction condition.

A flip-flop circuit including in combination first input circuit meansadapted to produce a signal at an output connection during theconcurrent occurrence of a first predetermined voltage level at firstand second input terminals;

first transistor having its base electrode connected to the outputconnection of the first input circuit means, its emitted electrodeconnected through a resistance to one source of reference potential, andits collector electrode connected through a resistance to another sourceof reference potential providing a voltage drop across the transistorand the series connected resistances, whereby output signals areprovided at the emitter electrode and the collector electrode during theoccurrence of a signal at the output connection of the first inputcircuit means;

first voltage setting transistor, first voltage setting transistorcircuit means connecting the base electrode of the first voltage settingtransistor to the collector electrode of the first transistor, thecollector electrode of the first voltage setting transistor to saidother source of reference potential, and the emitter electrode of thefirst voltage setting transistor to a first output terminal, andoperable to bias the first voltage second voltage setting transistor,second voltage setting transistor circuit means connecting the baseelectrode of the second voltage setting transistor to circuit meansconnecting the base electrode of the second output transistor to theemitter electrode of the second transistor, the collector electrode ofthe second output transistor to the second output terminal, and theemitter electrode of the second output transistor to a source ofreference potential, and operable to bias the second output transistorto provide a high impedance between the second output terminal and saidlast-mentioned source of reference 1. setting transistor to produce thefirst predetermined potential during the absence of an output signal atvoltage level at the output terminal during the the emitter electrode ofthe second transistor, and absence of an output signal at the collectorelectrode to provide a low impedance path between the second of thefirst transistor; output terminal and said last-mentioned source offirst output transistor, first output transistor circuit referencepotential-during the occurrence of an outmeans connecting the baseelectrode of the first output signal at the emitter electrode of thesecond put transistor to the emitter electrode of the first transistorthus providing the second predetermined transistor, the collectorelectrode of the first output voltage level at the second outputterminal; transistor to the first output terminal, and the emitter saidsecond voltage setting transistor circuit means electrode of the firstoutput transistor to a source 20 being operable to bias the secondvoltage setting of reference potential, and operable to bias thetransistor to initiate conduction therethrough in first outputtransistor to provide a high impedance response to the absence of anoutput signal at the between the first output terminal and saidlastcollector electrode of the second transistor and the mentionedsource of reference potential during the presence of the secondpredetermined voltage level absence of an output signal at the emitterelectrode at the second output terminal and restore the voltage of thefisrt transistor, and to provide a low impedance vel at the secondoutput terminal to the first prepath between the first output terminaland said lastdetermined voltage level, and operable to bias the Imentioned source reference potential during the second voltage settingtransistor to non-conduction occurrence of an output signal at theemitter elecin response to restoration of the first predetermined trodeof the first transistor thus producing a second voltage level at thesecond output terminal; predetermined voltage level at the first outputa connection from the first output terminal to the first termin l; inputterminal of the second input circuit means for said first voltagesetting transistor circuit means being pplying t Voltage level at theoutput terminal operable to bias the first voltage setting transistor tothe input terminal; to initiate conduction therethrough in response toconnection from the second output terminal to the the absence of anoutput signal at the collector elecfirst input terminal of the firstinput circuit means trode of the first transistor and the presence ofthe for pp y the Voltage level at h outPllt terminal secondpredetermined voltage level at the first outto the input terminal; putterminal and restore the voltage level at the first first input gatemeans connected to the second t routput terminal to the firstpredetermined Voltage minal 0f the first input circuit means,-said firstinput level, and operable to bias the first voltage setting gate meansbeing adapted to maintain the s nd transistor to non-conduction inresponse to restorainput terminal at the first predetermined Voltagelevel tion of the first predetermined voltage level at the and alsohelrlg adaPted to Produce a m m n ry first output terminal;. charge inthe voltage level at the input terminal asecond input circuitmeansadapted to producea signal from the first predetermined Voltagelevel to the at an output connection during the concurrent occursecondpredetermined Voltage level; and rence of the first predeterminedvoltage level at second input gate means connected the s nd fi t dsecond i t t i l terminal of the second input circuit means, said asecond transistor having its base electrode connected second input gmeans being adaPted to maintain to the output connection of the secondinput circuit the second input terminal a t first predetermined means,its emitter electrode connected through a Voltage level and'also beingadapted to produce a resistance -to the one source of referencepotential, momentary change in the voltage level at the input and itscollector electrode connected through a resistterminal from the firstpredetermined voltage level to ance to said other source ofreference'potential proh d predetermined voltage lgveL viding a voltagedrop across the transistor and the. series connected resistances,whereby output signals Reterences Cited by the Examiner are produced atthe emitter electrode and the collector electrodes during the occuranceof a signal UNITED STATES PATENTS at the output connection of the secondinput circuit 2,901,638 8/1959 Huang 307-885 means; 3,009,070 11/1961Barnes 307-88 5 OTHER REFERENCES Kellett: Elliott Scheffer StrokesElectronic Engineering (mag), September 1960, pages 534 to 539, pages535, 536, and 537 relied on.

Epsco Bulletin TDC-112, Power Amplifier, November the collectorelectrode of the second transistor, the collector electrode of thesecond voltage setting transistor to said other source of referencepotential, and the emitter electrode of the second voltage set- 1958, (1Sheet with 2 Sides Side 1 relied on) ting transistor to a second outputterminal, and A t RCA h 1N t TN N operable to bias the second voltagesetting transistor 'ronson e a ec 0 to produce-the first'predeterminedvoltage level at Redd August 1957 (1 Page) 7 the output terminal duringthe absence of an output GEORGE N WESTBY, Primary Examiner.

signal at the collector electrode of the second I transistor; ARTHURGAUSS, D. D. FORRER, Assistant Examiners.

1. A LOGIC CIRCUIT INCLUDING IN COMBINATION AN INPUT CIRCUIT MEANSADAPTED TO PRODUCE A SIGNAL IN RESPONSE TO A PREDETERMINED SIGNALCONDITION AT THE INPUT THERETO, A FIRST TRANSISTOR CIRCUIT MEANSCONNECTED TO SAID INPUT CIRCUIT MEANS AND RESPONSIVE TO SAID SIGNAL TOPRODUCE SIGNALS AT FIRST AND SECOND OUTPUT CONNECTIONS, A SECONDTRANSISTOR CIRCUIT MEANS INCLUDING A SECOND TRANSISTOR CONNECTED TO THEFIRST OF SAID OUTPUT CONNECTIONS, AND OUTPUT TERMINAL, AND A SOURCE OFREFERENCE POTENTIAL, AND RESPONSIVE TO THE SIGNAL AT THE FIRST OF SAIDOUTPUT CONNECTIONS TO BIAS THE SECOND TRANSISTOR TO CONDUCTION ANDCHANGE THE COLTAGE LEVEL AT THE OUTPUT TERMINAL FROM A FIRSTPEDETERMINED VOLTAGE LEVEL TO A SECOND PREDETERMINED VOLTAGE LEVEL, ANDA THIRD TRANSISTOR CIRCUIT MEANS INCLUDING A THIRD TRANSISTOR CONNECTORTO THE SECOND OF SAID OUTPUT CONNECTIONS AND TO SAID OUTPUT TERMINAL ANDRESPONSIVE TO TERMINATION OF THE SIGNAL AT THE SECOND OF SAID OUTPUTCONNECTIONS TO BIAS THE THIRD TRANSISTOR TO CONDUCTION AND CHANGE THEVOLTAGE LEVEL AT THE OUTPUT TERMINAL FROM SAID SECOND PREDETERMINEDVOLTAGE LEVEL TO SAID FIRST PREDETERMINED VOLTAGE LEVEL, AND RESPONSIVETO RESTORATION OF SAID FIRST PREDETERMINED VOLTAGE LEVEL AT THE OUTPUTTERMINAL TO BIAS THE THIRD TRANSISTOR TO NON-CONDUCTION.